Aditya Bedekar

Summary

PhD student in Computer Science and Engineering at UC Santa Cruz, specializing in hardware security, device modeling and reliability, advised by Dr.Dustin Richmond.

Research experience includes thesis work on BTI modeling using TCAD and SPICE to analyze device aging, timing degradation, and security vulnerabilities.

Experience

Visiting Scholar, Imec, Leuven, Belgium

June 2026 - September 2026

Calibrated physics-informed compact models to analyse gate leakage mechanisms for 2 nm GAAFET Nanosheet using GTS TCAD and SPICE.
Performed a detailed analysis across a range of geometries and temperatures of the nanosheet, to study the effects on gate leakage and captured these in the compact model.

Graduate Student Researcher, Hardware Systems Collective, UC Santa Cruz

Oct 2025 – June 2026

Worked on building FinFET structures using open-source literature, to analyse degradation in SPICE, based on physics-aware & accurate TCAD structures.
Gained hands-on experience with Virtual Fabrication and Process Engineering scripts using Synopsys Sentaurus TCAD.
Built a diverse repository of FinFET structures that can be used for physics-aware analysis of degradation in FinFETs, with variations in Epitaxy, Materials, Source-Drain Engineering.
Led advanced BTI reliability modeling at sub-7nm nodes by building scalable SPICE workflows for 7nm FinFET and 3nm GAAFET standard cells across temperature and stress corners.

Graduate Researcher, Hardware Systems Collective, UC Santa Cruz

Jul 2024 – Jun 2025

Developed a TCAD-based workflow (Synopsys Sentaurus) to model BTI-induced threshold voltage shifts in 7nm FinFET architectures, including stress and recovery.
Integrated SPICE-based tools (PySpice, Xyce, HSPICE MOSRA) to characterize circuit-level aging, enabling clock-to-Q delay analysis in Sky130 standard cells.
Simulated PMOS/NMOS degradation under varying stress voltages and temperatures, quantifying BTI impact on timing reliability.
Investigated hardware security implications of BTI, identifying side-channel vulnerabilities in FPGA fabrics due to NBTI-induced degradation.

Education

University of California, Santa Cruz

PhD, Computer Science and Engineering (Sept 2025 – Expected 06/28) Coursework: Semiconductor Physics, Nano Electronics, Semiconductor Reliability, TCAD Device and Process Technology

Master of Science, Computer Science and Engineering (Sept 2023 – Jun 2025)
Coursework: Computer Architecture, Digital Design, VLSI, Machine Learning, Digital Signal Processing.
Hands-on with FPGA design (Lattice iCE40), Sky130 PDK, ASAP 7 PDK, and RTL-to-GDSII flows.

University of Mumbai

Bachelor of Engineering, Electronics (Aug 2019 – Jun 2023)
Coursework: Digital Logic Circuits, Computer Networks, VLSI Design.
Built foundational skills in logic design, networking, and VLSI through lab projects.