Aditya Bedekar

Resume: https://drive.google.com/file/d/136NfDdkpXh04hR8Stes1l2Gx4POXvdTK/view?usp=sharing

Linkedin: https://www.linkedin.com/in/aditya-bedekar/

Work Experience

Graduate Student Researcher, Hardware Systems Collective, UC Santa Cruz

Oct 2025 – Dec 2025
Focused on circuit reliability and hardware security. Currently working on TDDB (Time Dependent Dielectric Breakdown).

Graduate Researcher, Hardware Systems Collective, UC Santa Cruz

Jul 2024 – Jun 2025

• Developed a TCAD-based workflow (Synopsys Sentaurus) to model BTI-induced threshold voltage shifts in 7nm FinFET architectures, including stress and recovery.
• Integrated SPICE-based tools (PySpice, Xyce, HSPICE MOSRA) to characterize circuit-level aging, enabling clock-to-Q delay analysis in Sky130 standard cells.
• Simulated PMOS/NMOS degradation under varying stress voltages and temperatures, quantifying BTI impact on timing reliability.
• Investigated hardware security implications of BTI, identifying side-channel vulnerabilities in FPGA fabrics due to NBTI-induced degradation.

Teaching Assistant, UC Santa Cruz

Jan 2024 – Jun 2025

• Led lab sections for 100+ students in Advanced Computer Networks and Introduction to Networking.
• Covered TCP/IP, VLAN, OSI model, LAN security, Layer 2 & Layer 3 switches, OSPF, BGP, HSRP, VRRP, BPDU, PortFast.
• Assisted with coursework, grading, and developed a QR-based attendance system to improve class efficiency.

Intern, Godrej & Boyce

Summer 2022

• Implemented data acquisition from industrial sensors using Modbus and UART.
• Achieved real-time visualization on HMI devices via RS-232.

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Education

University of California, Santa Cruz

PhD, Computer Science and Engineering (Sept 2025 – )

Master of Science, Computer Science and Engineering (Sept 2023 – Jun 2025)
Coursework: Computer Architecture, Digital Design, VLSI, Machine Learning, Digital Signal Processing.
Hands-on with FPGA design (Lattice iCE40), Sky130 PDK, ASAP 7 PDK, and RTL-to-GDSII flows.

University of Mumbai

Bachelor of Engineering, Electronics (Aug 2019 – Jun 2023)
Coursework: Digital Logic Circuits, Computer Networks, VLSI Design.
Built foundational skills in logic design, networking, and VLSI through lab projects.

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Projects

Local RAG Assistant for SPICE & TCAD Workflows

• Built a local RAG workflow with LangChain, FAISS, and HuggingFace embeddings to query 8,000+ pages of SPICE/TCAD documentation.
• Integrated offline LLM inference (Mistral, Llama3) with vector search to provide fact-grounded answers for reliability simulations (BTI, HCI, TDDB).
• Improved engineering productivity by reducing query time from hours to seconds, with responses citing page numbers and references.

Cache Performance Optimization Using ESESC Simulator

• Simulated and optimized the LZW compression algorithm on a single-core RISC-V processor.
• Reduced L2 cache miss rate from 99.8% to 58% and improved IPC from 0.26 to 0.44 (1.69×).
• Analyzed cache bottlenecks and identified optimization strategies for L1/L2 configurations.

Logic Design, Synthesis, and Verification on FPGA

• Designed logic systems on the Lattice iCE40 FPGA, incorporating AXI, memory, LUTs, and DSP operations.
• Built optimized FIFO and MAC units and performed functional and formal verification with open-source toolchains.
• Executed PnR and CDC verification across multiple clock domains.